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INTEGRATED CIRCUITS
DATA SHEET
TDA9144 I2C-bus controlled, alignment-free PAL/NTSC/SECAM decoder/sync processor with PALplus helper demodulator
Preliminary specification File under Integrated Circuits, IC02 1996 Jan 17
Philips Semiconductors
Preliminary specification
I2C-bus controlled, alignment-free PAL/NTSC/SECAM decoder/sync processor with PALplus helper demodulator
FEATURES * Multi-standard colour decoder and sync processor for PAL, NTSC and SECAM * PALplus helper demodulator * PALplus helper blanking and EDTV-2 blanking * I2C-bus controlled * I2C-bus addresses hardware selectable * Pin compatible with TDA9141 * Alignment free * Few external components * Designed for use with baseband delay lines * Integrated video filters * Adjustable luminance delay * Noise detector with I2C-bus read-out * Norm/no_norm detector with I2C-bus read-out * CVBS or Y/C input, with automatic detection possibility * CVBS output provided I2C-bus address 8A is used * Vertical divider system * Two-level sandcastle signal * VA synchronization pulse (3-state) * HA synchronization pulse or clamping pulse CLP input/output * Line-locked clock output (6.75 MHz or 6.875 MHz) or stand-alone I2C-bus output port * Stand-alone I2C-bus input/output port * Colour matrix and fast YUV switch * Comb filter enable input/output with subcarrier frequency * Internal bypass mode of external delay line for PALplus and NTSC applications * Low power standby mode with 3-state YUV outputs * Fast blanking detector with I2C-bus read-out * Blanked or unblanked sync on Yout by I2C-bus bit BSY * internal MACROVISION gating for the horizontal PLL enabled by bus bit EMG. ORDERING INFORMATION TYPE NUMBER TDA9144 PACKAGE NAME SDIP32 DESCRIPTION plastic shrink dual in-line package; 32 leads (400 mil) GENERAL DESCRIPTION
TDA9144
The TDA9144 is an I2C-bus controlled, alignment-free PAL/NTSC/SECAM decoder/sync processor with helper demodulator for PALplus signals and blanking facilities for PALplus and EDTV-2 signals. The TDA9144 has been designed for use with baseband chrominance delay lines, and has a combined subcarrier frequency/comb filter enable signal for communication with a PAL/NTSC comb filter. The IC can process both CVBS input signals and Y/C input signals. The input signal is available on an output pin, in the event of a Y/C signal, it is added into a CVBS signal. The sync processor provides a two-level sandcastle, a horizontal pulse (CLP or HA pulse, bus selectable) and a vertical (VA) pulse. When the HA pulse is selected, a line-locked clock (LLC) signal is available at the output port pin (6.75 MHz or 6.875 MHz). A fast switch can select either the internal Y signal with the UV input signals, or YUV signals made of the RGB input signals. The RGB input signals can be clamped with either the internal or an external clamping signal. Two pins with an input/output port and an output port of the I2C-bus are available. The I2C-bus address of the TDA9144 is hardware programmable. The TDA9144 is pin compatible with the TDA9141 (multistandard decoder/sync processor).
VERSION SOT232-1
1996 Jan 17
2
Philips Semiconductors
Preliminary specification
I2C-bus controlled, alignment-free PAL/NTSC/SECAM decoder/sync processor with PALplus helper demodulator
QUICK REFERENCE DATA SYMBOL VCC ICC VCVBS(p-p) VY(p-p) VC(p-p) VY(out) VY(out) VY(out)(p-p) VU(out)(p-p) VV(out)(p-p) VSC(bl) VSC(clamp) VVA VHA VLLC(p-p) VR,G,B(p-p) Vclamp(I/O) Vsub(p-p) VOPORT PARAMETER positive supply voltage supply current CVBS input voltage (peak-to-peak value) luminance input voltage (peak-to-peak value) chrominance burst input voltage (peak-to-peak value) luminance black-white output voltage luminance PALplus output voltage maximum luminance helper signal output voltage (peak-to-peak value) U output voltage (peak-to-peak value) V output voltage (peak-to-peak value) sandcastle blanking voltage level sandcastle clamping voltage level VA output voltage HA output voltage LLC output voltage amplitude (peak-to-peak value) RGB input voltage (peak-to-peak value) clamping pulse input/output voltage subcarrier output voltage amplitude (peak-to-peak value) port output voltage 0 to 100% saturation standard colour bar standard colour bar black-white top sync-white top sync-white CONDITIONS MIN. 7.2 50 - - - - - - - - 2.2 4.2 4.0 4.0 250 - - 150 4.0 TYP. 8.0 60 1.0 1.0 0.3 1.0 0.8 686 1.33 1.05 2.5 4.5 5.0 5.0 500 0.7 5.0 200 5.0
TDA9144
MAX. 8.8 70 1.43 1.43 0.6 - - - - - 2.8 4.8 5.5 5.5 - 1.0 - 300 5.5
UNIT V mA V V V V V mV V V V V V V mV V V mV V
1996 Jan 17
3
1996 Jan 17
SDA 6 SCL 5 VCC 7 HPLL 24 SC 10 VA 22 ADDR (CVBS) 15 LCA O PORT/LLC 16 SYNC SEPARATOR HORIZONTAL PLL I2C-BUS VERTICAL SYNC SEPARATOR HA TIMING GENERATOR CLP I/O PORT 26 Y/CVBS
BLOCK DIAGRAM
Philips Semiconductors
TRAP
handbook, full pagewidth
I2C-bus controlled, alignment-free PAL/NTSC/SECAM decoder/sync processor with PALplus helper demodulator
VA CLP/HA 11 17
R
G
B
F Uout Vout Yout 18 14 13 12
21 20 19
3 MATRIX ECL ECL YH1-YH0 DELAY TB YD3-YD0 BPS SWITCH 4
Uin Vin
DELAY 2 2 32 1
SECref -(R-Y) -(B-Y)
4
C DEC
Y CLAMP
SECAM CLOCHE
FILTER TUNING
SECAM DEMOD
SWITCH
2
helper
25
CHROMA SWITCH INA-INB
ACC
CHROMA BANDPASS
CHROMA PLL
HUE
PAL/NTSC DEMOD
8
BIAS
TDA9144
28 FILTref 27 AGND 29 CPLL 30 XTAL 31
ECMB
FSC BUFFER 23
IDENT SYSTEM
9 DGND
XTAL2
MBG897
Preliminary specification
Fscomb
TDA9144
Fig.1 Block diagram.
Philips Semiconductors
Preliminary specification
I2C-bus controlled, alignment-free PAL/NTSC/SECAM decoder/sync processor with PALplus helper demodulator
PINNING SYMBOL -(R-Y) -(B-Y) Uin Vin SCL SDA VCC DEC DGND SC VA Yout Vout Uout I/O PORT O PORT/LLC CLP/HA PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 DESCRIPTION output signal for -(R-Y) output signal for -(B-Y) chrominance U input chrominance V input serial clock input serial data input/output positive supply voltage digital supply decoupling digital ground sandcastle output vertical acquisition synchronization pulse luminance output chrominance V output chrominance U output input/output port output port/line-locked clock output clamping pulse/HA synchronization pulse input/output fast switch select input BLUE input GREEN input RED input I2C-bus output) Fscomb HPLL C Y/CVBS AGND FILTref CPLL XTAL XTAL2 SECref 23 24 25 26 27 28 29 30 31 32 comb filter status input/output horizontal PLL filter chrominance input luminance/CVBS input analog ground filter reference decoupling colour PLL filter reference crystal input second crystal input SECAM reference decoupling Fig.2 Pin configuration. address input (CVBS
handbook, halfpage
TDA9144
-(R-Y) -(B-Y) Uin Vin SCL SDA VCC DEC DGND
1 2 3 4 5 6 7 8
32 SECref 31 XTAL2 30 XTAL 29 CPLL 28 FILTref 27 AGND 26 Y/CVBS 25 C
TDA9144
9 24 HPLL 23 Fscomb 22 ADDR (CVBS) 21 R 20 G 19 B 18 F 17 CLP/HA
MBG896
SC 10 VA 11 Yout 12 Vout 13 Uout 14 I/O PORT 15 O PORT/LLC 16
F B G R ADDR (CVBS)
18 19 20 21 22
1996 Jan 17
5
Philips Semiconductors
Preliminary specification
I2C-bus controlled, alignment-free PAL/NTSC/SECAM decoder/sync processor with PALplus helper demodulator
FUNCTIONAL DESCRIPTION The TDA9144 is an controlled, alignment-free PAL/NTSC/SECAM colour decoder/sync processor which has been designed for use with baseband chrominance delay lines. For PALplus signals, helper demodulation and blanking facilities are included; for EDTV-2 (60 Hz) signals only blanking facilities are included. In the standard operating mode the I2C-bus address is 8A. If the address input is connected to the positive supply rail the address will change to 8E. Input switch Standard identification CAUTION The voltage on the chrominance pin must never exceed 5.5 V. If it does, the IC enters a test mode. The TDA9144 has a two pin input for CVBS or Y/C signals which can be selected via the I2C-bus. The input selector also has a position in which it automatically detects whether a CVBS or Y/C signal is on the input. In this input selector position, standard identification first takes place on an added Y/CVBS and C input signal. After that, both chrominance signal input amplitudes are checked once and the input with the strongest chrominance burst signal is selected. The input switch status is read out by the I2C-bus via output bit YC. The auto input detect mode indicates YC = 1 for a VBS input signal (no chrominance component). CVBS output In the standard operating mode with I2C-bus address 8A, a CVBS output signal is available on the address pin, which represents either the CVBS input signal or the Y/C input signal, added into a CVBS signal. RGB colour matrix CAUTION The voltage on the Uin pin must never exceed 5.5 V. If it does, the IC enters a test mode. The TDA9144 has a colour matrix to convert RGB input signals into YUV signals. A fast switch, controlled by the signal on pin F and enabled by I2C-bus via EFS (enable fast switch), can select between these YUV signals and the YUV signals of the decoder. Mode FRGB = 1 (forced RGB) overrules EFS and forces the matrixed RGB inputs to the YUV outputs. 1996 Jan 17 6 I2C-bus
TDA9144
The Y signal is internally connected to the switch. The -(R-Y) and -(B-Y) output signals of the decoder first have to be delayed in external baseband chrominance delay lines. The outputs of the delay lines must be connected to the UV input pins. If the RGB signals are not synchronous with the selected decoder input signal, clamping of the RGB input signals is possible by I2C-bus selection of ECL (external RGB clamp mode) and by feeding an external clamping signal to the CLP pin. Also in external RGB clamp mode the VA output will be in a high impedance OFF-state. The YUV outputs can be put in 3-state mode by bus bit LPS (low power standby mode).
The standards which the TDA9144 can decode depend upon the choice of external crystals. If a 4.4 MHz and a 3.6 MHz crystal are used then SECAM, PAL 4.4/3.6 and NTSC 4.4/3.6 can be decoded. If two 3.6 MHz crystals are used then only PAL 3.6 and NTSC 3.6 can be decoded. Which 3.6 MHz standards can be decoded depends upon the exact frequencies of the 3.6 MHz crystals. In an application where not all standards are required only one crystal is sufficient; in this instance the crystal must be connected to the reference crystal input (pin 30). If a 4.4 MHz crystal is used it must always be connected to the reference crystal input. Both crystals are used to provide a reference for the filters and the horizontal PLL, however, only the reference crystal is used to provide a reference for the SECAM demodulator. To enable the calibrating circuits to be adjusted exactly, two bits from I2C-bus subaddress 00 are used to indicate which crystals are connected to the IC. The standard identification circuit is a digital circuit without external components. The search loop is illustrated in Fig.3. The decoder (via the I2C-bus) can be forced to decode either SECAM or PAL/NTSC (but not PAL or NTSC). Crystal selection can also be forced. Information concerning standard and which crystal is selected and whether the colour killer is ON or OFF is provided by the read out. Using the forced-mode does not affect the search loop, it does however, prevent the decoder from reaching or staying in an unwanted state. The identification circuit skips impossible standards (e.g. SECAM when no 4.4 MHz crystal is fitted) and illegal standards (e.g. in forced mode). To reduce the risk of wrong identification PAL has priority over SECAM. Only line identification is used for SECAM. For a vertical frequency of 60 Hz SECAM can be blocked to prevent wrong identification by means of bus bit SAF.
Philips Semiconductors
Preliminary specification
I2C-bus controlled, alignment-free PAL/NTSC/SECAM decoder/sync processor with PALplus helper demodulator
TDA9144
handbook, full pagewidth
SECAM
c c c
PAL
KILLED
SECAM
KILLED
c
NTSC c
NTSC
KILLED
PAL
KILLED
PAL c
c c c c c NTSC
KILLED
PAL
PAL
KILLED
NTSC
Reference crystal
Second crystal
MGE040
Fig.3 Search loop of the identification circuit.
Integrated filters All chrominance bandpass and notch filters, including the luminance delay line, are an integral part of the IC. The filters are gyrator-capacitor type filters. The resonant frequency of the filters is controlled by a circuit that uses the active crystal to tune the SECAM Cloche filter during the vertical flyback time. The remaining filters and the luminance delay line are matched to this filter. The filters can be switched to either 4.43 MHz, 4.29 MHz or 3.58 MHz. The switching is controlled by the standard identification circuit. The luminance notch used for SECAM has a lower Q-factor than the notch used for PAL/NTSC. The notches are provided with a little preshoot to obtain a symmetrical step response. In Y/C mode the chrominance notch filters are bypassed, to preserve full signal bandwidth. For a CVBS signal the chrominance notch filters can be bypassed by bus selection of bit TB (trap bypass). 1996 Jan 17 7
The luminance to helper delay difference can be adjusted by I2C-bus, to achieve a correct fitting for the delay in the PALplus helper demodulation signal path and the luminance path (not for helper only with trap). The delay of the colour difference signals -(R-Y) and -(B-Y) in the chrominance signal path and the external chrominance delay lines when used, can be fitted to the luminance signal delay control via I2C-bus in 40 ns steps. The typical luminance delay can be calculated: delay 90 + SAKSBK {170 + 40(FRQTB)} + 160(YD3) + 160(YD2) + 80(YD1) + 40(YD0) [ns].
Philips Semiconductors
Preliminary specification
I2C-bus controlled, alignment-free PAL/NTSC/SECAM decoder/sync processor with PALplus helper demodulator
Colour decoder The PAL/NTSC demodulator employs an oscillator that can operate with either crystal (3.6 MHz or 4.4 MHz). If the I2C-bus indicates that only one crystal is connected it will always connect to the crystal on the reference crystal input (pin 30). The Hue signal which is adjustable by I2C-bus, is gated during the burst for NTSC signals. The SECAM demodulator is an auto-calibrating PLL demodulator which has two references. The reference crystal, to force the PLL to the desired free-running frequency and the bandgap reference, to obtain the correct absolute value of the output signal. The VCO of the PLL is calibrated during each vertical blanking period, when the IC is in search mode or SECAM mode. If the reference crystal is not 4.4 MHz the decoder will not produce the correct SECAM signals. Especially for PALplus and NTSC applications, an internal bypass mode of the external baseband delay line (for instance TDA4665) is added, controlled by bus bit BPS (bypass mode) and has a gain of 2. The bypass mode is not available for SECAM. Comb filter interfacing The frequency of the active crystal is fed to the Fscomb output, which can be connected to an external comb filter IC (e.g. SAA4961). When bus bit ECMB is LOW, the subcarrier frequency is suppressed and its DC value is LOW. With ECMB HIGH, the DC value is HIGH with the subcarrier frequency present, and I2C-bus output bit YC and the input switch are always forced in the Y/C mode, unless an external current sink (e.g. from the comb filter) prevents this, as pin Fscomb also acts as input pin. In this event the subcarrier frequency is still present on the same DC HIGH level PALplus helper demodulation PALplus has been introduced to come to an evolutionary introduction of wide screen transmissions with backward
TDA9144
compatibility with PAL 4 : 3 TV sets. A PALplus signal has the format of a standard analog PAL composite signal containing 430 PAL picture lines in letter box format (lines 60 to 274 and 372 to 586), together with helper information contained in the black bands above and below the visible letter box area (lines 24 to 59, 336 to 371, 275 to 310, and 587 to 622). A viewer with a 4 : 3 TV set will see a letter box picture: black bars of 18 picture height at the top as well as at the bottom with a 16 : 9 picture in between (see left-hand side picture of Fig.4). A wide screen viewer without PALplus decoder will only see the centre picture of Fig.4, or the right hand side picture when a zoom option is available, however with only 430 lines of vertical resolution. When a wide screen viewer has a PALplus decoder, it expands the letter box format to a full-size wide screen picture with a vertical resolution of 574 lines. The decoder uses the helper lines information, hidden within the black bars. See the right-hand side picture of Fig.4. Furthermore a PALplus signal will deliver full luminance bandwidth by an Y/C separation technique called `Motion Adaptive Colour Plus' (MACP). Using this technique, the signal becomes free from cross colour and cross luminance. This algorithm requires MACP pre-processing in the PALplus encoder at the studio output. The PALplus parts which the TDA9144 processes are in short: * Helper demodulation and multiplexing helper with letter box luminance signal * Chrominance trap bypassing if necessary * Creation of reference line 22 (see Fig.5) * Creation of black set-up and helper set-up * Correct blanking and timing reference for the necessary post processing ICs.
handbook, full pagewidth
helper lines 430 picture lines helper lines
MBG903
574 picture lines
Fig.4 Possible PALplus picture displays.
1996 Jan 17
8
Philips Semiconductors
Preliminary specification
I2C-bus controlled, alignment-free PAL/NTSC/SECAM decoder/sync processor with PALplus helper demodulator
In case of a PALplus input signal, the standard identification system of the TDA9144 only determines PAL and needs additional I2C-bus information for PALplus, via bus bits MACP, HD, HOB and HBC. Bus bit MACP determines whether the 4.43 chrominance signal component of the CVBS input signal should be suppressed by a 4.43 trap or not. For MACP = 1 the chrominance suppression takes place outside the TDA9144. The HD bit (helper demodulation) enables PALplus helper demodulation on the U phase (i.e. the B-Y demodulation axis). As there is only a 4.43 notch for the demodulated helper, an external notch filter is necessary to suppress the 8.86 MHz demodulation product and resolve the baseband helper signal. The demodulated helper luminance signal is always led to a notch filter (4.43 MHz, no bypass here), then multiplexed with the regular 430 letter box lines luminance signal and led to the output Yout. The black level of the luminance signal is internally clamped with a large time constant to the black level generated by the helper demodulator. Also bus bits HD and MACP determine the presence of a black set-up voltage (with luminance scaling of a factor 0.8) and a helper set-up voltage for the demodulated helper signal on the output signal Yout. These set-up voltages are necessary for PALplus signal post processing outside the TDA9144. The set-up voltages are also multiplexed into a reference line 22, combined with the demodulated helper reference of line 23 and luminance reference of line 623, both present in every PALplus signal for correct PALplus reference post processing (see Fig.5). Additional helper blanking bits (HOB, HBC) determine whether the helper signal has to be blanked or blanked conditionally depending on the signal-to-noise ratio bit SNR. Helper blanking can only take place on a norm sync signal, indicated by output bit NRM = 1. Table 1 is valid in 50 Hz or 60 Hz mode. Table 1 HOB 0 1 1 1 Helper blanking modes HBC X 0 1 1 SNR X X 0 1 HELPER BLANKING OFF ON OFF ON
TDA9144
230 to 312 and 493 to 49(1) when helper blanking is activated. The TDA9144 can handle PALplus signals in either CVBS or Y/C format. In case of a Y/C signal, the modulated helper must be available on the chrominance input pin (C). The use of the 4.43 trap will not be necessary, as the chrominance and luminance components of a Y/C signal are already separated, so the 4.43 trap for the letter box luminance is bypassed (not for the demodulated helper signal). During helper demodulation, the internal chroma bandpass filter is bypassed. For PALplus the I2C-bus Hue bits HU0 to HU5 are used to adjust for a correct helper demodulator phase. This has no effect on the R-Y and B-Y demodulator phase for PAL. Table 2 gives an overview of the possible PALplus modes and their effects in the TDA9144. The table is only valid for a 50 Hz system. In 60 Hz system mode the columns for line 22, 23b and 623a do not exist, and using the MACP and HD bits has no effect on the 60 Hz signal. * Mode 1 normal PAL * Mode 2 PAL with MACP processing * Mode 3 full PALplus * Mode 4 PALplus without MACP processing (helper only) * Mode 5 near_norm or no_norm sync condition * Mode 6 norm sync condition with fast blanking active * Mode 7 system ident not identified as PAL. The indications a and b for the lines 22, 23 and 623 respectively stand for the first half and the second half of a line. The signalling bits in line 23 (see Fig.5) are processed in the same manner as letter box luminance lines in the TDA9144. Signalling bit decoding and PALplus identification is done externally with I2C-bus as communication link to the TDA9144 for bus bits MACP, HD, HOB, and HBC.
For EDTV-2 (system M, 60 Hz, 525 lines) outside the letter box area, blanking is possible and takes place on lines 1996 Jan 17 9
(1) For system M the line numbers start with the first equalizing pulse in field 1, but the internal line counter starts counting at the first vertical sync pulse in field 1. This line number notation is used here and in Fig.9.
Philips Semiconductors
Preliminary specification
I2C-bus controlled, alignment-free PAL/NTSC/SECAM decoder/sync processor with PALplus helper demodulator
TDA9144
1.00 handbook, full pagewidth (V) line 623 20 s 10.5 s 0.30 10 s
white level reference PALplus CVBS in
1.00 (V)
0.30
0 input signals 1.00 line 23 0.80 (V) 0.45 0.30 0.15 0
32 s
0
,,,, ,,, ,,,,,, ,,,, ,,,,,, ,,, ,, ,,, ,, ,,
EBU colour bar 10.5 s 52 s max. modulated helper line
1.00 (V) black level reference helper reference burst -U phase 0.45 0.30 PALplus signalling bits 41 s 51 s 10.83 s 0.15 0
1.00 (V) 0.60
line 623
white level reference
1.00 (V)
Yout (pin 12)
0.60
800 mV
Y black 0.20 0 0.4 s black (clamp level)
black set-up 0.20 black level offset
(1)
0
1.00 (V) 0.77 output signals 0.60 line 23
1.00 helper set-up (V) B 0.60
,,, ,,,, ,,,, ,,,,,, ,,, ,, ,,,,,, ,,,,, ,, ,, ,
(2)
EBU colour bar with black set-up
686 mV
demodulated helper area limits
0.20 0
0.4 s PALplus signalling bits
demodulated helper reference
0.20 0
(4)
0.15 s CLP to set up
52 s
0.65 s
1.00 (V) 0.60
mid-grey offset = A - B(3) line 22 reference line helper set-up (mid-grey) 212 LLC pulses 30.8 s black set-up 11.2 s 0.15 s A 22 s 151 LLC pulses
delay
baseband helper line with black and helper set-up
MBG904
0.20 0
52 s
(1) (2) (3) (4)
See Y output parameter Vos in Section "Characteristics" See demodulated helper parameter td in Section "Characteristics" See demodulated helper parameter Vos in Section "Characteristics" See CLP output/HA output parameter td in Section "Characteristics"
0.65 s
Figures drawn when using subaddress 8A and an Ydelay of 440 ns. LLC frequency equals 6.875 MHz; 440 LLC pulses per horizontal line. Demodulated helper shown when using an external 8.8 notch filter.
Fig.5 PALplus CVBS input and Y output signals.
1996 Jan 17
10
1996 Jan 17 11
Philips Semiconductors
Table 2
PALplus modes for 50 Hz
I2C-bus controlled, alignment-free PAL/NTSC/SECAM decoder/sync processor with PALplus helper demodulator
MODE MACP HD
NRM
FBA PAL
4.43 TRAP TB(3) bypass bypass(6) TB(7) TB(3) TB(3) TB(3)
COMB ENABLE ECMB disabled disabled ECMB ECMB ECMB
LUMA BLACK HELPER DELAY AMPL HELPER SET-UP(1) SET-UP(2) LINE (b-w) LINES (mV) (mV) (V) BPS BPS bypass BPS BPS BPS 1 0.8 0.8 0.8 1 1 1 0 200 200 200 0 0 0 0 0 400 400 0 0 0 luma(4) luma(4) helper(4) helper(4) luma luma(4) luma(4)
LINE 22 black set-up set-up set-up black black black
LINE 23b black helper(5) helper helper black black black
LINE 623a black luma luma luma luma(9) black black
1 2 3 4 5 6 7 Notes
0 1 1 0 X X X
0 0 1 1 X X X
1 1 1 1 0 1 1
0 0 0 0 X 1 X
1 1 1 1 X X 0
disabled(8) bypass
1. When activated, the black set-up is added to the full frame. 2. When activated, the helper set-up is added to line 22b, 23b, 24 to 59, 275 to 310, 336 to 371, 587 to 622. 3. The 4.43 MHz trap is active in CVBS input mode and TB = 0, otherwise the trap is bypassed. 4. When helper blanking is active (see Table 1) lines 24 to 59, 275 to 310, 336 to 371, 587 to 622 are blanked. 5. Demodulated helper with 400 mV set-up and 4.43 MHz trap active. 6. The 4.43 MHz trap is bypassed during the letter box lines, but activated during helper lines and line 23b to reduce 4.43 MHz rest carrier. 7. The 4.43 MHz trap is active during helper lines and line 23b, during the letter box lines the trap is active when TB = 0. 8. In principle the comb filter should be enabled during letter box lines, when ECMB = 1. It depends on the comb filter if this will be implemented. 9. Line 623a contains luminance in NO_NORM, line 623a is black in a NEAR_NORM sync condition.
Preliminary specification
TDA9144
Philips Semiconductors
Preliminary specification
I2C-bus controlled, alignment-free PAL/NTSC/SECAM decoder/sync processor with PALplus helper demodulator
Fast blanking detector For PALplus it is necessary to switch-off PALplus as soon as an external RGB input signal is mixed into a PALplus signal via a switching signal on the fast blanking input (F). To detect the presence of a fast blanking signal, a circuit is added which forces the MACP and HD bit to zero if in more than one line per field a blanking pulse is detected. More than one line per field is chosen to prevent switching-off at every spike detected on the fast blanking input. The detector output FBA (fast blanking active) can be read-out by the I2C-bus. Blanked/unblanked sync By means of the I2C-bus bit BSY (blanked sync), output signal Yout will be presented with or without its composite sync part. At BSY = 0 the composite sync is present on Yout. When activated, helper blanking takes place only during helper lines scan. At BSY = 1 the black level is filled in during the line blanking interval and vertical blanking interval. When activated, the helper blanking extends the vertical blanking. For PALplus modes with black set-up no composite sync will be present on Yout, independent of the BSY condition. Sync processor (1 loop) The main part of the sync circuit is an oscillator running at 440 x fH (6.875 MHz), provided that I2C-bus address 8A is used or 432 x fH (6.75 MHz) for 8E. Its frequency is divided by 440 or 432 to lock the 1 loop to the incoming signal. The time-constant of the loop can be selected by the I2C-bus (fast, auto or slow). In the fast mode the fast time-constant is chosen independent of signal conditions. In auto mode the medium time-constant is present with a fast time constant during the vertical retrace period ('field boost'). If the noise detector indicates a noisy video signal the time-constant switches to slow with a smaller field boost, which is also the time-constant for the slow mode. In case of a slow time constant sync gating takes place in a 6 s window around the separated sync pulse. In case of no sync lock, both the auto and the slow mode have a medium time constant, to ensure reliable catching. The noise content of the video signal is determined by a noise detector circuit. This circuit measures the noise at top sync during a 15 line period every field (65 lines after start VA pulse). When the noise level supersedes the detector threshold in two consecutive fields, noise is indicated and bus bit SNR is set. The free-running frequency of the oscillator is determined by a digital control circuit that is locked to the active crystal.
TDA9144
When a power-on-reset pulse is detected the frequency of the oscillator is switched to a frequency of about 10 MHz (23 kHz horizontal frequency) to protect the horizontal output transistor. The oscillator frequency is calibrated to 6.875 MHz or 6.75 MHz after receiving data on subaddress 01 for the first time after power-on-reset detection. To ensure that this procedure does not fail it is absolutely necessary to send subaddress 00 before subaddress 01. Subaddress 00 contains the crystal indication bits and when subaddress 01 is received the line oscillator calibration will be initiated (for the start-up procedure after power-on-reset detection, see the I2C-bus protocol). The calibration is terminated when the oscillator frequency reaches 6.875 MHz or 6.75 MHz. The 1 loop can be opened using the I2C-bus. This is to facilitate On Screen Display (OSD) information. If there is no input signal or a very noisy input signal, the 1 loop can be opened to provide a stable line frequency, and thus a stable picture. The sync part also delivers a two-level sandcastle signal, which provides a combined horizontal and vertical blanking signal and a clamping pulse for the display section of the TV. MACROVISION sync gating A dedicated gating signal for the separated sync pulses, starting 11 lines after the detection of a vertical sync pulse until picture scan starts, can be used to improve the behaviour of the horizontal PLL with respect to the unwanted disturbances caused by the pseudo-sync pulses in video signals with MACROVISION anti-copy guard signals. This sync gating excludes the pseudo-sync pulses and can only take place in the auto and fast 1 time constant mode, provided I2C-bus bit SNR = 0 and I2C-bus
1996 Jan 17
12
Philips Semiconductors
Preliminary specification
I2C-bus controlled, alignment-free PAL/NTSC/SECAM decoder/sync processor with PALplus helper demodulator
bit EMG = 1. I2C-bus bit EMG = 1 enables and EMG = 0 disables this sync gating in the horizontal PLL. Vertical divider system The vertical divider system has a fully integrated vertical sync separator. The divider can accommodate both 50 Hz and 60 Hz systems; it can either determine the field frequency automatically or it can be forced to the desired system via the I2C-bus. A block diagram of the vertical divider system is illustrated in Fig.6. The divider system operates at twice the horizontal frequency. The line counter receives enable pulses at this frequency, thereby counting two pulses per line. A state diagram of the controller is shown in Fig.7. Because it is symmetrical only the right-hand part will be described.
TDA9144
When the controller returns to the COUNT state, the line counter will be reset half a line after the start of the vertical sync pulse of the video input signal. The NORM window normally looks within one line width and a sudden half line delay of the vertical sync pulse change can therefore be neglected, but for PALplus conditions every half line shift of the vertical sync pulse must be detected. In this case a half line window is used. When the controller is in the NEAR_NORM state it will move to the COUNT state if it detects the vertical sync pulse within the NEAR_NORM window (i.e. 622 < LC < 628). If no vertical sync pulse is detected the controller will move back to the COUNT state when the line counter reaches LC = 628. The line counter will then be reset. When the controller is in the NO_NORM state, it will move to the COUNT state when it detects a vertical sync pulse and reset the line counter. If a vertical sync pulse is not detected before LC = 722 (if the 1 loop is locked, even in forced mode) it will move to the COUNT state and reset the line counter. If the 1 loop is not locked the controller will return to the COUNT state when LC = 628. The forced mode option keeps the controller in either the left-hand side (60 Hz) or the right-hand side (50 Hz) of the state diagram. Figure 8 illustrates the state diagram of the norm counter which is an up/down counter that increases its counter value by 1 if it finds a vertical sync pulse within the selected window. If not it decreases the counter value by 1 (or 2, see Fig.8). In the NEAR_NORM and NORM states the first correct vertical sync pulse after one or more incorrect vertical sync pulses is processed as an incorrect pulse. This procedure prevents the system from staying in the NEAR_NORM or NORM state if the vertical sync pulse is correct in the first field and incorrect in the second field. In case of no sync lock (SLN = 1) the norm counter is reset to NO_NORM (wide search window), for fast vertical catching when switching between video sources. Fast switching between different channels however can still result in a continuous horizontal sync lock situation, when the channel is changed before the norm counter has reached the NORM state. To provide faster vertical catching in this case, measures have been taken to prevent the norm counter to count down to zero before reaching the NO_NORM state (see left-hand of Fig.8). Bus bit FWW (forced wide window) enables the norm counter to stay in the NO_NORM state if desired. The norm/no_norm status is read out by bus bit NRM.
handbook, halfpage
LINE COUNTER
CONTROLLER
TIMING GENERATOR
NORM COUNTER
MGE043
Fig.6 Block diagram of the vertical divider system.
Depending on the previously found vertical frequency, the controller will be in one of the COUNT states. When the line counter has counted 488 pulses (i.e. 244 lines of the video input signal), the controller will move to the next state depending on the output of the norm counter. This can be either NORM, NEAR_NORM or NO_NORM, depending on the position of the vertical sync pulse in the previous fields. When the controller is in the NORM state it generates the vertical sync pulse (VSP) automatically and then, when the line counter is at LC = 626, moves to the WAIT state. In this condition it waits for the next pulse of the double line frequency signal, and then moves to the COUNT state of the current field frequency.
1996 Jan 17
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Philips Semiconductors
Preliminary specification
I2C-bus controlled, alignment-free PAL/NTSC/SECAM decoder/sync processor with PALplus helper demodulator
TDA9144
handbook, full pagewidth
else
NO NORM no_norm no_norm
LC = 528 or LC = 576 or on VSP LC = 628 or LC = 722 or on VSP
LC < 488 COUNT on SYNC if LC < 576 WAIT FOR RESET PULSE on SYNC if LC 576 COUNT
LC < 488
LC = 526 norm
LC = 626 norm
NORM near_norm LC 525
NORM near_norm LC 625
on VSP if 522 < LC < 528 or on LC = 528
NEAR NORM
NEAR NORM
on VSP if 622 < LC < 628 or on LC = 628
LC < 522
LC < 622
vertical frequency 60 Hz
vertical frequency 50 Hz
MGE042
Fig.7 State diagram of the vertical divider system.
1996 Jan 17
14
Philips Semiconductors
Preliminary specification
I2C-bus controlled, alignment-free PAL/NTSC/SECAM decoder/sync processor with PALplus helper demodulator
TDA9144
handbook, full pagewidth
22 < NC 27
0 NC < 12
NORM
NC = 22 (RESET NC)
NO NORM
NC = 26
10 < NC < 26(1)
NC
NC = 17
NEAR NORM 10 < NC < 17
(R
ES
NC = 14
ET
= 10 NC )
NEAR NORM
0 = 1 C) NC T N E ES (R
NC = 0
NC = 12
NEAR NORM 0 < NC < 14
norm test area
near_norm test area
MGE041
(1) VSP found: count 1 up; no VSP found: count 2 down.
Fig.8 State diagram of the norm counter.
1996 Jan 17
15
Philips Semiconductors
Preliminary specification
I2C-bus controlled, alignment-free PAL/NTSC/SECAM decoder/sync processor with PALplus helper demodulator
Output port and in/output port Two stand-alone ports are available for external use. These ports are I2C-bus controlled, the output port by bus bit OPB and the input/output port by bus bit OPA. Bus bit OPA is an open-drain output, to enable input port functionality. The pin status is read out by bus via output bit IP. Sandcastle
TDA9144
Figure 9 illustrates the timing of the acquisition sandcastle (ASC) and the VA pulse with respect to the input signal. The sandcastle signal is according to the two-level 5 V sandcastle format. An external vertical guard current can overrule the sink current to enable blanking purposes.
2nd handbook, full pagewidth FIELD 625
1st FIELD
50 Hz
23
ASC VA 1st FIELD 312
(1)
2nd FIELD
336
ASC
2nd FIELD 525
1st FIELD
60 Hz
17
ASC VA
1st FIELD 262
2nd FIELD
280
ASC
MBG902
(1) See Vertical Section in "Characteristics"
Fig.9 Acquisition sandcastle signal and VA pulse timing diagram.
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Philips Semiconductors
Preliminary specification
I2C-bus controlled, alignment-free PAL/NTSC/SECAM decoder/sync processor with PALplus helper demodulator
I2C-bus
TDA9144
For address 8A, an unconnected pin 22 is sufficient as this pin is also a CVBS output. Do not short-circuit the input to ground. If the address input is connected to the positive supply rail, the address changes from 8A to 8E. Table 3 Slave address (8A) A6 1 A5 0 A4 0 A3 0 A2 1 A1 X A0 1 R/W X
SLAVE ADDRESS 8A
Valid subaddresses: 00 to 03 and 17 to 18 (Hex). Only the five least significant bits of the subaddress bytes are recognized. Auto-increment mode available for subaddresses. The output addresses 00 and 01 can only be read in auto-increment mode. The I2C-bus transceiver is designed for a maximum clock frequency (fSCL) of 100 kHz. Table 4 Input bytes MSB D7 INA FORF EFS LCA . MACP BPS D6 INB FORS ECL FWW . HD LPS D5 TB OPA HU5 - . HOB FRGB DATA BYTE D4 ECMB OPB HU4 - . HBC EMG D3 FOA POC HU3 - . BSY YD3 D2 FOB FM HU2 - . YH2 YD2 D1 XA SAF HU1 - . YH1 YD1 LSB D0 XB FRQF HU0 - . - YD0
SUB ADDRESS 00 01 02 03 . 17 18 Table 5
Output (status) bytes D7 POR - D6 FSI - D5 YC - D4 SL FBA D3 IP NRM D2 SAK SNR D1 SBK SXA D0 FRQ SXB
OUTPUT ADDRESS 00 01
Start up procedure: read the status byte until POR = 0; send subaddress 18 with the LPS bit indicating normal operation (LPS = 0); send subaddress 00 with the crystal indicator bits (XA and XB) indicating that only one crystal is connected to the IC(1); wait for 50 ms; send subaddress 01; wait for at least 50 ms; set XA,XB to the actual crystal configuration. Each time before the data in the IC is refreshed, the status byte must be read. If POR = 1, then the above procedure must be carried out to restart the IC. As long as POR = 1, sending subaddress 01 does not start the line oscillator calibration. POR is reset when the status register is read out and can only be reset when the supply voltages exceed the POR detection levels mentioned in the Bias Generator characteristics (see Chapter "Characteristics"). Failure to stick to the above procedure may result in an incorrect horizontal frequency after power-up or a power-dip. Remark: if the presence of output signals HA/CLP and/or VA is required after power-up of the IC, subaddress 02 with the ECL bit indicating ECL = 0 must be sent before sending subaddress 00.
(1) To be absolutely sure that the line oscillator is calibrated with the appropriate crystal frequency data, it is possible to check the received values of the crystal indication bits via status bits SXA and SXB.
1996 Jan 17
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Philips Semiconductors
Preliminary specification
I2C-bus controlled, alignment-free PAL/NTSC/SECAM decoder/sync processor with PALplus helper demodulator
INPUT SIGNALS Table 6 INA 0 0 1 Note 1. When ECMB = 1 and no current is drawn from the Fscomb pin, source select is forced to be YC. Table 7 TB 0 1 Note 1. The chrominance trap is always bypassed in YC mode or when MACP = 1. Table 8 ECMB 0 1 Note 1. MACP = 1 or HD = 1 always enforces ECMB = 0. Table 9 FOA 0 0 1 1 time constant FOB 0 1 - auto slow fast Note MODE Comb filter enable; note 1 CONDITION comb filter disabled comb filter enabled trap bypassed Trap bypass; note 1 CONDITION trap not bypassed OPB 0 1 LOW HIGH LEVEL Source select; note 1 INB 0 1 - CVBS YC auto CVBS / YC SOURCE Table 11 Forced field frequency FORF 0 0 1 1 FORS 0 1 0 1 60 Hz 50 Hz
TDA9144
FIELD FREQUENCY auto; 60 Hz if no lock
auto; 50 Hz if no lock
Table 12 Output value I/O port OPA 0 1 LOW HIGH LEVEL
Table 13 Output value O port
Table 14 1 loop control POC 0 1 1 loop closed 1 loop open CONDITION
Table 15 Forced standard; note 1 FM 0 1 1 1 1 SAF - 0 0 1 1 FRQF - 0 1 0 1 STANDARD auto search PAL/NTSC second crystal PAL/NTSC reference crystal black and white SECAM reference crystal
Table 10 Crystal indication XA 0 0 1 1 XB 0 1 0 1 CRYSTAL 2 x 3.6 MHz 1 x 3.6 MHz 1 x 4.4 MHz 1 x 3.6 MHz and 1 x 4.4 MHz
1. If XA and XB indicate that only one crystal is connected to the IC and FM and FRQF force it to use the second crystal, then colour will be switched off. When SAF = 0, SECAM 60 Hz is disabled; when SAF = 1, SECAM 60 Hz is enabled. Table 16 Enable fast switch EFS 0 1 CONDITION fast switch disabled fast switch enabled, when FRGB = 0
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Philips Semiconductors
Preliminary specification
I2C-bus controlled, alignment-free PAL/NTSC/SECAM decoder/sync processor with PALplus helper demodulator
Table 17 External RGB clamp mode ECL 0 1 CONDITION off; internal clamp pulse is used on; external clamp pulse has to be supplied to CLP pin Note
TDA9144
Table 24 PALplus helper demodulator active; note 1 HD 0 1 off on, PALplus mode with helper set-up 400 mV and black set-up 200 mV CONDITION
Table 18 Forced RGB mode FRGB 0 1 forced RGB CONDITION YUV, when disabled via EFS
1. Black set-up and helper set-up will only be present in a norm sync condition. Table 25 PALplus/EDTV-2 helper blanking (Y, U, V) HOB HBC - 0 1 1 SNR - - 0 1 BLANKING off on off on
Table 19 YUV outputs as a function of EFS, FRGB and Fast switch F EFS 0 - 1 1 Table 20 Hue FUNCTION Hue ADDRESS HU5 to HU0 DIGITAL NUMBER 000000 = -45 111111 = +45 Table 21 Line-locked clock active LCA 0 1 LLC/HA mode CONDITION OPB/CLP mode Note FRGB 0 1 0 0 F - - 0 1 SELECTED INPUTS YUV RGB YUV RGB
0 1 1 1
Table 26 Blanked sync on Yout BSY 0 1 blanked sync CONDITION unblanked sync; note 1
1. Except for PALplus with black set-up. Table 27 Luminance to helper delay control YH2 to YH1 00 11 -20 ns +25 ns CONDITION
Table 22 Forced wide window FWW 0 1 CONDITION auto window mode forced wide window
Table 28 Baseband delay line bypass; note 1 BPS 0 1 Note no bypass baseband delay line bypassed CONDITION
Table 23 Motion Adaptive Colour Plus; note 1 MACP 0 1 Note 1. Black set-up will only be present in a norm sync condition. 1996 Jan 17 19 CONDITION internal 4.43 notch used external MACP chrominance filtering used, 4.43 notch bypassed, black set-up 200 mV
1. When HD = 1 the baseband delay line is forced into bypass mode. SECAM cannot be bypassed. Table 29 Low power standby mode LPS 0 1 CONDITION normal operation low power standby
Philips Semiconductors
Preliminary specification
I2C-bus controlled, alignment-free PAL/NTSC/SECAM decoder/sync processor with PALplus helper demodulator
Table 30 Enable MACROVISION gating EMG 0 1 disable gating enable gating CONDITION Table 37 Standard read-out SAK 0 0 0 Table 31 Luminance delay control YD3 to YD0 0000 1111 OUTPUT SIGNALS Table 32 Power-on reset POR 0 1 normal mode power-down mode CONDITION -280 ns +160 ns CONDITION 0 1 1 1 SBK 0 0 1 1 0 0 1 FRQ 0 1 0 1 0 1 -
TDA9144
STANDARD PAL second crystal PAL reference crystal NTSC second crystal NTSC reference crystal illegal forced mode SECAM reference crystal colour off
Table 38 Fast blanking active FBA 0 1 CONDITION no fast blanking detected fast blanking detected
Table 39 Norm/no_norm indication in vertical divider system NRM 0 1 norm CONDITION no_norm or near_norm
Table 33 Field frequency indication FSI 0 1 50 Hz 60 Hz CONDITION
Table 40 Signal-to-noise ratio Table 34 Input switch mode YC 0 1 CVBS mode Y/C mode Table 41 Crystal indication read-out Table 35 1 lock indication SL 0 1 not locked locked CONDITION SXA 0 0 1 1 Table 36 Input value I/O port IP 0 1 LOW HIGH LEVEL SXB 0 1 0 1 CRYSTAL 2 x 3.6 MHz 1 x 3.6 MHz 1 x 4.4 MHz 1 x 3.6 MHz and 1 x 4.4 MHz CONDITION SNR 0 1 S/N > 20 dB S/N < 20 dB CONDITION
1996 Jan 17
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Philips Semiconductors
Preliminary specification
I2C-bus controlled, alignment-free PAL/NTSC/SECAM decoder/sync processor with PALplus helper demodulator
LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL VCC ICC Ptot Tstg Tamb PARAMETER supply voltage supply current total power dissipation storage temperature operating ambient temperature CONDITIONS - - - -55 -10 MIN. - - - - - TYP.
TDA9144
MAX. 9.0 70 630 +150 +70
UNIT V mA mW C C
THERMAL CHARACTERISTICS SYMBOL Rth j-a PARAMETER thermal resistance from junction to ambient in free air 48 VALUE K/W UNIT
QUALITY SPECIFICATION Quality level in accordance with "SNW-FQ-611-E" is applicable for ESD protection, human body model: 3000 V, 100 pF, 1500 on all pins. Machine model: 300 V, 200 pF, 0 on all pins. The number of the quality specification can be found in the "Quality Reference Handbook". The handbook can be ordered using the code 9397 750 00192.
1996 Jan 17
21
Philips Semiconductors
Preliminary specification
I2C-bus controlled, alignment-free PAL/NTSC/SECAM decoder/sync processor with PALplus helper demodulator
CHARACTERISTICS VCC = 8 V; Tamb = 25 C; I2C-bus address 8A; unless otherwise specified. SYMBOL Supply (pin 7) VCC ICC Ptot ICC Input switch Caution: the voltage on pin 25 must never exceed 5.5 V, if it does, the IC enters a test mode Y/CVBS INPUT (PIN 26) Vi(p-p) Zi Ci Ii(bias) Vi(p-p) Zi Ci Vo(p-p) Zo B Vtsl VD(DEC) Vdet(CC) Vdet(DEC) IL(DEC) input voltage (peak-to-peak value) input impedance input capacitance input bias current top sync-white - 60 - - - 60 - top sync-white CL = 15 pF - - 7 2.2 1.0 - - 3.3 supply voltage supply current total power dissipation low power supply current 7.2 50 360 12 8.0 60 480 16 PARAMETER CONDITIONS MIN. TYP.
TDA9144
MAX.
UNIT
8.8 70 620 22
V mA mW mA
1.43 - 5 - 0.6 - 5 - 500 - 3.4
V k pF A V k pF
C INPUT (PIN 25) input burst voltage (peak-to-peak value) input impedance input capacitance 0.3 - - 1.0 - - 2.8
CVBS OUTPUT (PIN 22); ONLY FOR ADDRESS 8A output voltage (peak-to-peak value) output impedance bandwidth at -3 dB top-sync voltage level V MHz V
Bias generator (pin 8) digital supply voltage POR detection level for power supply POR detection level for DEC pin current load on digital supply sum of pins 8, 11, 16, 17 4.8 5.7 4.0 - 5.0 6.0 4.3 - 5.2 6.3 4.6 2.0 V V V mA
Subcarrier regeneration GENERAL; note 1 CR catching and holding range reference crystal second crystal Zi phase shift for 80% deviation of catching range input impedance reference crystal and second crystal 0.80 1.00 1.20 k 500 450 - - - - - - 5 Hz Hz deg
1996 Jan 17
22
Philips Semiconductors
Preliminary specification
I2C-bus controlled, alignment-free PAL/NTSC/SECAM decoder/sync processor with PALplus helper demodulator
SYMBOL FSCOMB OUTPUT (PIN 23) Vsub(p-p) Vcen Vcdis Isink RGND ACC ACC control range change of -(R-Y) and -(B-Y) signals over range colour killer treshold PAL/NTSC SECAM kill/unkill hysteresis -34 -31 - -31 -28 3 -20 - - - subcarrier output voltage amplitude (peak-to-peak value) comb enable voltage level comb disable voltage level sink current to undo forced Y/C mode of input switch value of grounded resistor to undo forced Y/C mode of input switch CL = 15 pF 150 4.0 - 0.4 4 200 4.2 0.1 - - PARAMETER CONDITIONS MIN. TYP.
TDA9144
MAX.
UNIT
300 5.0 1.4 1.0 10
mV V V mA k
+6 1
dB dB
-28 -25 -
dB dB dB
Demodulators; -(R-Y) and -(B-Y) outputs (pins 1 and 2); demodulated Yhelper (pin 12) GENERAL ratio of -(B-Y) to -(R-Y) TC temperature coefficient of -(R-Y) and -(B-Y) amplitude spread of -(R-Y) to -(B-Y) ratio between standards V-(R-Y) V-(B-Y) B Zo VCC V-(R-Y)(p-p) V-(B-Y)(p-p) Vres(p-p) Vres(p-p) Vres(p-p) S/N output level of -(R-Y) output during blanking level output level of -(B-Y) output during blanking level bandwidth at -3 dB output impedance supply voltage dependence hue phase shift -(R-Y) output voltage (peak-to-peak value) -(B-Y) output voltage (peak-to-peak value) note 3 standard colour bar 1.20 - -1 1.7 1.7 600 - - 35 480 610 - - - 46 1.27 - - 2.1 2.0 670 - - 45 540 685 - - - - 1.34 0.1 +1 2.5 2.5 750 500 2 55 605 765 15 20 tbf - %/K dB V V kHz %/V deg
PAL/NTSC DEMODULATOR standard colour bar standard colour bar mV mV mV mV mV dB
8.8 MHz residue (peak-to-peak value) both outputs 7.2 MHz residue (peak-to-peak value) both outputs 4.4 and 3.6 MHz residue signal-to-noise ratio both outputs 0 to 1 MHz
1996 Jan 17
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Philips Semiconductors
Preliminary specification
I2C-bus controlled, alignment-free PAL/NTSC/SECAM decoder/sync processor with PALplus helper demodulator
SYMBOL PAL DEMODULATOR VR(p-p) V-(R-Y)(p-p) V-(B-Y)(p-p) fos S/N Vres(p-p) fpole Vcal NL
1 2H
TDA9144
PARAMETER
CONDITIONS
MIN. - -
TYP. - - 1.08 1.37 - - - 85 3 4 - 686 400 - - - - - - - 52.8 8.8 30.8 2.6
MAX.
UNIT
ripple (peak-to-peak value)
20 5
mV deg
demodulator phase error -(R-Y) output voltage (peak-to-peak value) -(B-Y) output voltage (peak-to-peak value) black level offset frequency signal-to-noise ratio 7.8 MHz to 9.4 MHz residue (peak-to-peak value) pole frequency of de-emphasis ratio of pole and zero frequency calibration voltage non linearity 0 to 1 MHz
SECAM DEMODULATOR standard colour bar standard colour bar 0.96 1.22 - 40 - 77 - 3 - PALplus limits only helper lines, line 22 and line 23 within passband including
1 2H
1.21 1.53 7 - 30 93 - 5 3
V V kHz dB mV kHz V %
DEMODULATED HELPER (PIN 12) VY(p-p) VY(p-p) td c(M/D) helper output voltage (peak-to-peak value) helper set-up amplitude group delay demodulator phase crosstalk modulated helper to demodulated sign 4.43 MHz residue THD tY Vos tsu td td B Filters TUNING Vtune tuning voltage 1.5 3 6 V total harmonic distortion in ACC helper output timing to Yout offset demodulator mid-grey to inserted mid-grey level helper set-up width (363 LLC pulses) and start helper set-up delay between mid-sync of input and start helper set-up delay between start black set-up and start helper set-up (212 LLC pulses) baseband helper bandwidth at -3 dB YD3 to YD0 = 1011; note 4; see Fig.5 only line 22 and 23 mid-grey line 23 and line 22; see Fig.5 610 380 - - -36 -36 -36 - - - - - - 770 420 10 5 - - - 10 5 - - - - mV mV ns deg dB dB dB ns mV s s s MHz
error
0 to 1 MHz
1996 Jan 17
24
Philips Semiconductors
Preliminary specification
I2C-bus controlled, alignment-free PAL/NTSC/SECAM decoder/sync processor with PALplus helper demodulator
SYMBOL PARAMETER CONDITIONS MIN. TYP.
TDA9144
MAX.
UNIT
LUMINANCE DELAY; YD3 to YD0 = 1011; YH2 to YH1 = 01 td(on) delay time colour on fsc = 3.6 MHz; TB = 0 fsc = 3.6 MHz and 4.4 MHz; TB = 1 td(off) td(tun) td(tun) fo delay time colour off delay time tuning range Y to helper delay tuning range 15 steps YD3 to YD0; note 2 3 steps YH2 to YH1 555 515 350 -280 -20 3.53 4.37 4.23 2.60 3.20 2.90 26 580 540 370 - - 3.58 4.43 4.29 not active 2.80 3.50 3.15 - 3.58 4.43 1.20 1.40 3.00 3.80 3.50 - 3.76 4.65 1.35 1.55 MHz MHz MHz dB 605 565 390 +160 +25 ns ns ns ns ns
CHROMINANCE TRAP notch frequency fsc = 3.6 MHz fsc = 4.4 MHz SECAM Y/C and B/W mode B bandwidth at -3 dB fsc = 3.6 MHz fsc = 4.4 MHz SECAM fsc(sup) fres B subcarrier suppression CHROMINANCE BANDPASS resonant frequency bandwidth at -3 dB fsc = 3.6 MHz fsc = 4.4 MHz fsc = 3.6 MHz fsc = 4.4 MHz CLOCHE FILTER fres B resonant frequency bandwidth at -3 dB SECAM SECAM 4.26 241 4.29 268 4.31 295 MHz kHz 3.40 4.21 1.05 1.25 MHz MHz MHz MHz 3.63 4.49 4.35 MHz MHz MHz
Sync input (pin 26) VIDEO INPUT VY/CVBS(p-p) sync pulse amplitude (peak-to-peak value) slicing level td Nth H td delay of sync pulse due to internal filter noise detector threshold level hysteresis delay between internally separated vertical sync pulse and video signal 35 40 0.2 18 2 12 300 47 0.3 20 3 18.5 600 55 0.4 22 5 27 mV % s dB dB s
1996 Jan 17
25
Philips Semiconductors
Preliminary specification
I2C-bus controlled, alignment-free PAL/NTSC/SECAM decoder/sync processor with PALplus helper demodulator
SYMBOL Horizontal section CLP OUTPUT (OPB/CLP MODE); HA OUTPUT (LLC/HA) MODE (BOTH ON PIN 17) VOH VOL Isink Isource tW(HA) td tW td td f VCC fCR fHR fo HIGH level output voltage LOW level output voltage sink current source current HA pulse width (32 LLC pulses) delay between middle of horizontal sync pulse and middle of HA CLP pulse width (25 LLC pulses) delay start CLP pulse to start black set-up (33 LLC pulses + Y delay) delay between middle of horizontal sync pulse and start of CLP pulse 6 jitter HD = 1 or MACP = 1; YD3 to YD0 = 1011; see Fig.5 note 4 1 in auto mode note 4 4.0 - 2 2 - 0.3 - - 3.0 - - - 625 - - 5 0.2 - - 4.65 0.45 3.65 5.35 3.2 - - 40 - - - PARAMETER CONDITIONS MIN. TYP.
TDA9144
MAX.
UNIT
5.5 0.4 - - - 0.6 - - 3.4 5
V V mA mA s s s s s ns
FIRST LOOP (1) frequency deviation when not locked supply voltage dependence catching range holding range static phase shift 1.5 - - 1.0 0.1 % Hz/V Hz kHz s/kHz
LLC OUTPUT (PIN 16); LLC/HA MODE output frequency 440 x fH 440 x fH Vo(p-p) Vo td output amplitude (peak-to-peak value) DC output voltage level delay between negative edge of LLC and positive edge of HA pulse CL = 15 pF 50 Hz standard 60 Hz standard - - 0.25 - 10 6.875 6.923 - 2.5 20 40 - - - MHz MHz V V ns
Vertical section VERTICAL OSCILLATOR ffr fLR LR free running frequency frequency locking range divider locking range FORF = 1; divider ratio 628 FORF = 0; divider ratio 528 - - 43 488 50 60 - 625 - - 64 722 Hz Hz Hz
1996 Jan 17
26
Philips Semiconductors
Preliminary specification
I2C-bus controlled, alignment-free PAL/NTSC/SECAM decoder/sync processor with PALplus helper demodulator
SYMBOL PARAMETER CONDITIONS MIN. TYP.
TDA9144
MAX.
UNIT
VA OUTPUT (PIN 11); ECL = 0 VOH VOL Isink Isource tW(VA) HIGH level output voltage LOW level output voltage sink current source current VA pulse width 2.5/fH 3/fH td Zo Vo Isink Vbl Isource Iext tW(H) td delay between start of vertical sync pulse and positive edge of VA output impedance 50 Hz standard 60 Hz standard note 5; see Fig.9 ECL = 1 - - - 3 160 192 35 - - - - - s s s M 4.0 - 2 2 5 0.2 - - 5.5 0.4 - - V V mA mA
Sandcastle output (pin 10) zero level output voltage sink current 0 0.5 0.5 0.7 1 0.9 V mA
HORIZONTAL AND VERTICAL BLANKING blanking voltage level source current external current required to force the output to the blanking level horizontal blanking pulse width delay between start of horizontal blanking and start of clamping pulse (69 LLC pulses) (44 LLC pulses) 2.2 0.5 1.0 - - 2.5 0.7 - 10.0 6.4 2.8 0.9 3.0 - - V mA mA s s
CLAMPING PULSE Vclamp Isource tW(clamp) td clamping voltage level source current clamping pulse width delay between middle sync of input and start of clamping pulse (25 LLC pulses) note 4 4.2 0.5 - 3.0 4.5 0.7 3.6 3.2 4.8 0.9 - 3.4 V mA s s
YUV/RGB switches Caution: the voltage on pin 3 must never exceed 5.5 V, if it does, the IC enters a test mode RGB INPUTS (PINS 21, 20 AND 19 RESPECTIVELY); note 6 Vi(p-p) Zi Ci Vi(p-p) Vi(p-p) Zi Ci input voltage (peak-to-peak value) input impedance input capacitance - 3 - - - 3 - 0.7 - - 1.33 1.05 - - 1 - 5 V M pF
UV INPUTS (PINS 3 AND 4 RESPECTIVELY); note 6 U input voltage (peak-to-peak value) V input voltage (peak-to-peak value) input impedance (both inputs) input capacitance (both inputs) 1.90 1.50 - 5 V V M pF
1996 Jan 17
27
Philips Semiconductors
Preliminary specification
I2C-bus controlled, alignment-free PAL/NTSC/SECAM decoder/sync processor with PALplus helper demodulator
SYMBOL Y OUTPUT (PIN 12) Vo(p-p) Vo(p-p) Zo Vo S/N Vout tW(black) td Vos Gv U output voltage PALplus output voltage output impedance DC output voltage level signal-to-noise ratio black set-up amplitude black set-up width delay between mid-sync of input and start black set-up offset voltage Yblack to re-inserted black voltage gain from Y/CVBSi to Yo from Y/CVBSi to Yo UV OUTPUTS (PINS 14 AND 13); note 6 Vo(p-p) Vo(p-p) Zo Vo Gv U output voltage (peak-to-peak value) V output voltage (peak-to-peak value) output impedance (both outputs) DC output voltage level voltage gain from Uin to Uout from Vin to Vout GENERAL Vdiff difference between black levels of YUV outputs in RGB mode and YUV mode non-linearity bandwidth at -3 dB crosstalk between RGB and UVin signals on UVout bandwidth at -1 dB internal Y clamping time constant sync locked mixed RGB/YUV - via fast blanking any input to any output any input to any output; CL = 15 pF f = 0 to 5 MHz any input to any output; CL = 15 pF - 7 - 5 - UV switched on RGB switched on between F and YUV 0 0.9 - - 0.94 0.94 0.97 0.97 - - - 2.3 1.33 1.05 - 2.6 MACP = 1 or HD = 1 1.35 1.08 1.43 1.14 black level f = 0 to 5 MHz MACP = 1 or HD = 1 363 LLC pulses YD3 to YD0 = 1011; note 4; see Fig.5 see Fig.5 black-white black-white - - - 2.7 - 190 - - - 1.00 0.80 - 3.0 52 200 52.8 8.8 - PARAMETER CONDITIONS MIN. TYP.
TDA9144
MAX. - - 250 3.3 - 210 - - 10
UNIT
V V V dB mV s s mV
1.50 1.20
1.90 1.50 250 2.9 1.00 1.00
V V V
10
mV
NL B c B tclamp VIL VIH td
- - - - 10 - - -
5 - -50 - - 0.5 3.0 20
% MHz dB MHz ms
FAST SWITCH F (PIN 18) LOW level input voltage HIGH level input voltage switching delay V V ns
1996 Jan 17
28
Philips Semiconductors
Preliminary specification
I2C-bus controlled, alignment-free PAL/NTSC/SECAM decoder/sync processor with PALplus helper demodulator
SYMBOL PARAMETER CONDITIONS MIN. TYP. - - 3.5 - -
TDA9144
MAX.
UNIT
EXTERNAL CLAMP INPUT (PIN 17) VIL VIH tW(clamp) Vos(clamp) Zi Gv LOW level input voltage (pin CLP) HIGH level input voltage (pin CLP) clamping pulse width clamping offset voltage on UV outputs input impedance ECL = 1 no clamping clamping note 7 0 2.4 1.8 - 3 0.6 5.5 - 10 - V V s mV M
Colour matrix voltage gain from R to Yout from G to Yout from B to Yout from R to Uout from G to Uout from B to Uout from R to Vout from G to Vout from B to Vout Output and in/output port O PORT (PIN 16); OPB/CLP MODE VOH VOL Isink Isource VOH VOL Isink VIH VIL HIGH level output voltage LOW level output voltage sink current source current 4.0 - 100 100 - - 2 2.0 - 5 0.2 - - - 0.2 - - - 5.5 0.4 - - VCC 0.4 - - 0.6 V V A A V V mA V V 0.41 0.80 0.15 0.41 0.80 1.21 0.95 0.80 0.15 0.43 0.84 0.16 0.43 0.84 1.27 1.00 0.84 0.16 0.45 0.88 0.17 0.45 0.88 1.33 1.05 0.88 0.17
I/O PORT; OPB/CLP MODE HIGH level output voltage LOW level output voltage sink current HIGH level input voltage LOW level input voltage
1996 Jan 17
29
Philips Semiconductors
Preliminary specification
I2C-bus controlled, alignment-free PAL/NTSC/SECAM decoder/sync processor with PALplus helper demodulator
Notes to the characteristics
TDA9144
1. All frequency variations are referred to 3.58 MHz or 4.43 MHz carrier frequency. All oscillator specifications are measured with the Philips crystal series 9920 520 0047x and 9920 520 0048x. The oscillator circuit is insensitive to the spurious responses of the crystal. The typical crystal parameters for the crystals mentioned above are: a) Load resonance frequency f0 = 4.433619 MHz or 3.579545 MHz (CL = 20 pF). b) Motional capacitance CM = 20.6 fF (4.43 MHz crystal) or 14.7 fF (3.58 MHz crystal). c) Parallel capacitance C0 = 5 pF for both crystals. d) The minimum detuning range can only be specified if both the IC and the crystal tolerances are known and the general specifications given for the subcarrier regeneration are therefore valid for the specified crystal series. In the figure tolerances of the crystal with respect to nominal frequency, motional capacitance and ageing have been taken into account and have been counted for by Gaussian addition. Whenever different typical crystal parameters are used, the following equation might be helpful for calculating the impact on the detuning capabilities: CM e) Detuning range proportional to: ------------------------- CO 2 1 + ------- CL f) The resulting detuning range should be corrected for temperature shift and supply deviation of both the IC and the crystal. For the above mentioned crystals, the actual load capacitance in the application should be CL = 18 pF to account for parasitic capacitance on and off chip. For 3-norm applications with two crystals connected to one pin, the maximum load capacitance of the crystal pin should not exceed 12 pF. 2. YD3 and YD2 are equal significant bits, both representing a 160 ns delay step. YD1 represents 80 ns and YD0 represents a 40 ns delay step. 3. The Hue control is active for NTSC on the -(R-Y) and -(B-Y) signals and for PALplus only on the demodulated helper signal. 4. This delay is partially caused by the low-pass filter at the sync separator input. 5. The delay between the positive edge of VA and the first negative edge of HA (or positive edge of CLP) after VA is 1 34.5 s for field 1 and 2.5 s for field 2 (17 LLC pulses with or without ------------- respectively). Especially for PALplus 2 x fH signals the regenerated VA pulses must have a fixed and known phase relation to the undisturbed V pulses of the incoming video signal. This relation must remain correct as long as the vertical divider is in norm mode (indirect sync mode), so the coincidence window used here must be a half line compared to the one line coincidence window used outside PALplus. With a well defined phase relation of the regenerated VA pulses to the regenerated HA pulses a correct field identification (odd/even) and all the required timing signals referring to a certain line in each frame can be generated externally in the PALplus decoder environment. 6. The output signals of the demodulator are called -(R-Y) and -(B-Y) in this specification. The colour difference input and output signals of the YUV switch are called UV signals. However, these signals do not have the amplitude correction factor of real UV signals. They are called UV signals and not -(R-Y) and -(B-Y) to prevent confusion between the colour difference signals of the demodulator and the colour difference signals of the YUV switch. 7. The maximum external clamping pulse width is the minimum available blanking level time of the supplied RGB signals.
1996 Jan 17
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1996 Jan 17
Y/CVBS 82 k 100 nF GND 18 pF 18 pF 3.3 nF 15 k 470 nF 3.3 nF C 75 75 100 nF 100 nF 100 nF 27 26 25 100 nF 24 32 31 30 29 28
TEST AND APPLICATION INFORMATION
Philips Semiconductors
handbook, full pagewidth
I2C-bus controlled, alignment-free PAL/NTSC/SECAM decoder/sync processor with PALplus helper demodulator
ADDR (CVBS) R G B F CLP/HA
Fscomb
75
75
75
75
100 nF 23 22 21 20
100 nF 19
100 nF 18 17
TDA9144
1 100 nF 100 F 8V 5V 2 100 nF 3 100 nF 4 100 nF 5 100 6 100 7 8 100 nF 9 10 11 12 13 14 15 16
31
240 5V1 100 nF 1
14 13 12 11 10 9 16 15 14 13 12 11 10 9 TDA4665 2 3 4 5 6 7 8 1 2 PC74HCU04 3 4 5 6
8 100 nF 7
1nF
120 k
LLC interface to TDA9151
SCL
SDA
SC
VA
Yout
Vout
Uout
O PORT/LLC I/O PORT
LCC
HA
MBG901
Preliminary specification
TDA9144
Pins 28 and 32 are sensitive to leakage currents. Keep the analog and digital ground currents well separated The decoupling capacitor between pin 8 and 9 must be placed as close to the IC as possible.
Fig.10 Application circuit.
Philips Semiconductors
Preliminary specification
I2C-bus controlled, alignment-free PAL/NTSC/SECAM decoder/sync processor with PALplus helper demodulator
EQUIVALENT PIN CIRCUITS PIN 1 SYMBOL -(R-Y) EQUIVALENT PIN CIRCUIT
TDA9144
100 0.2 mA
1
MGE046
2
-(B-Y)
100 0.2 mA
2
MGE047
3
Uin
0.07 mA
100 3
MGE048
1996 Jan 17
32
Philips Semiconductors
Preliminary specification
I2C-bus controlled, alignment-free PAL/NTSC/SECAM decoder/sync processor with PALplus helper demodulator
PIN 4 Vin
CLIN DCT 100 4 0.07 mA
TDA9144
SYMBOL
EQUIVALENT PIN CIRCUIT
MGE049
5
SCL
5
MGE050
6
SDA
6
MGE051
DATA
7
VCC
7
MGE052
8
DEC
5V
8
MGE053
1996 Jan 17
33
Philips Semiconductors
Preliminary specification
I2C-bus controlled, alignment-free PAL/NTSC/SECAM decoder/sync processor with PALplus helper demodulator
PIN 9 SYMBOL DGND EQUIVALENT PIN CIRCUIT
9
TDA9144
MGE054
10
SC
10
MGE055
11
VA
11
MGE056
12
Yout
100 0.5 mA
12
MGE057
1996 Jan 17
34
Philips Semiconductors
Preliminary specification
I2C-bus controlled, alignment-free PAL/NTSC/SECAM decoder/sync processor with PALplus helper demodulator
PIN 13 SYMBOL Vout EQUIVALENT PIN CIRCUIT
TDA9144
100 0.5 mA
13
MGE058
14
Uout
100 0.5 mA
14
MGE059
15
I/O PORT
15
MGE060
16
O PORT/LLC
100 16
MGE061
1996 Jan 17
35
Philips Semiconductors
Preliminary specification
I2C-bus controlled, alignment-free PAL/NTSC/SECAM decoder/sync processor with PALplus helper demodulator
PIN 17 SYMBOL CLP/HA EQUIVALENT PIN CIRCUIT
TDA9144
17
MGE062
18
F
100 18
MGE064
19 20 21
B G R
0 to 60 A
0 to 60 A
0 to 60 A
CLP 100 100 100
19
20
21
MGE063
1996 Jan 17
36
Philips Semiconductors
Preliminary specification
I2C-bus controlled, alignment-free PAL/NTSC/SECAM decoder/sync processor with PALplus helper demodulator
PIN 22 SYMBOL ADDR (CVBS) EQUIVALENT PIN CIRCUIT
TDA9144
100 0.5 mA
22
MGE065
23
Fscomb
100
23
MGE066
24
HPLL
4V
24
4V
MGE067
25
C
25
100 1 M
MGE068
1996 Jan 17
37
Philips Semiconductors
Preliminary specification
I2C-bus controlled, alignment-free PAL/NTSC/SECAM decoder/sync processor with PALplus helper demodulator
PIN 26 SYMBOL Y/CVBS EQUIVALENT PIN CIRCUIT
TDA9144
1 k 26 100
3.5 A
MGE069
27 28
AGND FILTref
analog ground
4V INIT 28
MGE071
29
CPLL
29
MGE072
1996 Jan 17
38
Philips Semiconductors
Preliminary specification
I2C-bus controlled, alignment-free PAL/NTSC/SECAM decoder/sync processor with PALplus helper demodulator
PIN 30 SYMBOL XTAL EQUIVALENT PIN CIRCUIT
TDA9144
1 k 0.2 mA
30
MGE073
31
XTAL2
1 k 0.2 mA
31
MGE074
32
SECref
32
CAL
MGE075
1996 Jan 17
39
Philips Semiconductors
Preliminary specification
I2C-bus controlled, alignment-free PAL/NTSC/SECAM decoder/sync processor with PALplus helper demodulator
PACKAGE OUTLINE SDIP32: plastic shrink dual in-line package; 32 leads (400 mil)
TDA9144
SOT232-1
D seating plane
ME
A2 A
L
A1 c Z e b 32 17 b1 wM (e 1) MH
pin 1 index E
1
16
0
5 scale
10 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 4.7 A1 min. 0.51 A2 max. 3.8 b 1.3 0.8 b1 0.53 0.40 c 0.32 0.23 D (1) 29.4 28.5 E (1) 9.1 8.7 e 1.778 e1 10.16 L 3.2 2.8 ME 10.7 10.2 MH 12.2 10.5 w 0.18 Z (1) max. 1.6
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT232-1 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION
ISSUE DATE 92-11-17 95-02-04
1996 Jan 17
40
Philips Semiconductors
Preliminary specification
I2C-bus controlled, alignment-free PAL/NTSC/SECAM decoder/sync processor with PALplus helper demodulator
SOLDERING Introduction There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "IC Package Databook" (order code 9398 652 90011). Soldering by dipping or by wave The maximum permissible temperature of the solder is 260 C; solder at this temperature must not be in contact with the joint for more than 5 seconds. The total contact DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values
TDA9144
time of successive solder waves must not exceed 5 seconds. The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (Tstg max). If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. Repairing soldered joints Apply a low voltage soldering iron (less than 24 V) to the lead(s) of the package, below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300 C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 and 400 C, contact may be up to 5 seconds.
This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011.
1996 Jan 17
41
Philips Semiconductors
Preliminary specification
I2C-bus controlled, alignment-free PAL/NTSC/SECAM decoder/sync processor with PALplus helper demodulator
NOTES
TDA9144
1996 Jan 17
42
Philips Semiconductors
Preliminary specification
I2C-bus controlled, alignment-free PAL/NTSC/SECAM decoder/sync processor with PALplus helper demodulator
NOTES
TDA9144
1996 Jan 17
43
Philips Semiconductors - a worldwide company
Argentina: IEROD, Av. Juramento 1992 - 14.b, (1428) BUENOS AIRES, Tel. (541)786 7633, Fax. (541)786 9367 Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. (02)805 4455, Fax. (02)805 4466 Austria: Triester Str. 64, A-1101 WIEN, P.O. Box 213, Tel. (01)60 101-1236, Fax. (01)60 101-1211 Belgium: Postbus 90050, 5600 PB EINDHOVEN, The Netherlands, Tel. (31)40-2783749, Fax. (31)40-2788399 Brazil: Rua do Rocio 220 - 5th floor, Suite 51, CEP: 04552-903-SAO PAULO-SP, Brazil, P.O. Box 7383 (01064-970), Tel. (011)821-2333, Fax. (011)829-1849 Canada: PHILIPS SEMICONDUCTORS/COMPONENTS: Tel. (800) 234-7381, Fax. (708) 296-8556 Chile: Av. Santa Maria 0760, SANTIAGO, Tel. (02)773 816, Fax. (02)777 6730 China/Hong Kong: 501 Hong Kong Industrial Technology Centre, 72 Tat Chee Avenue, Kowloon Tong, HONG KONG, Tel. (852)2319 7888, Fax. (852)2319 7700 Colombia: IPRELENSO LTDA, Carrera 21 No. 56-17, 77621 BOGOTA, Tel. (571)249 7624/(571)217 4609, Fax. (571)217 4549 Denmark: Prags Boulevard 80, PB 1919, DK-2300 COPENHAGEN S, Tel. (45)32 88 26 36, Fax. (45)31 57 19 49 Finland: Sinikalliontie 3, FIN-02630 ESPOO, Tel. (358)0-615 800, Fax. (358)0-61580 920 France: 4 Rue du Port-aux-Vins, BP317, 92156 SURESNES Cedex, Tel. (01)4099 6161, Fax. (01)4099 6427 Germany: P.O. Box 10 51 40, 20035 HAMBURG, Tel. (040)23 53 60, Fax. (040)23 53 63 00 Greece: No. 15, 25th March Street, GR 17778 TAVROS, Tel. (01)4894 339/4894 911, Fax. (01)4814 240 India: Philips INDIA Ltd, Shivsagar Estate, A Block, Dr. Annie Besant Rd. Worli, Bombay 400 018 Tel. (022)4938 541, Fax. (022)4938 722 Indonesia: Philips House, Jalan H.R. Rasuna Said Kav. 3-4, P.O. Box 4252, JAKARTA 12950, Tel. (021)5201 122, Fax. (021)5205 189 Ireland: Newstead, Clonskeagh, DUBLIN 14, Tel. (01)7640 000, Fax. (01)7640 200 Italy: PHILIPS SEMICONDUCTORS S.r.l., Piazza IV Novembre 3, 20124 MILANO, Tel. (0039)2 6752 2531, Fax. (0039)2 6752 2557 Japan: Philips Bldg 13-37, Kohnan 2 -chome, Minato-ku, TOKYO 108, Tel. (03)3740 5130, Fax. (03)3740 5077 Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL, Tel. (02)709-1412, Fax. (02)709-1415 Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR, Tel. (03)750 5214, Fax. (03)757 4880 Mexico: 5900 Gateway East, Suite 200, EL PASO, TX 79905, Tel. 9-5(800)234-7381, Fax. (708)296-8556 Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB, Tel. (040)2783749, Fax. (040)2788399 New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND, Tel. (09)849-4160, Fax. (09)849-7811 Norway: Box 1, Manglerud 0612, OSLO, Tel. (022)74 8000, Fax. (022)74 8341 Pakistan: Philips Electrical Industries of Pakistan Ltd., Exchange Bldg. ST-2/A, Block 9, KDA Scheme 5, Clifton, KARACHI 75600, Tel. (021)587 4641-49, Fax. (021)577035/5874546 Philippines: PHILIPS SEMICONDUCTORS PHILIPPINES Inc., 106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI, Metro MANILA, Tel. (63) 2 816 6380, Fax. (63) 2 817 3474 Portugal: PHILIPS PORTUGUESA, S.A., Rua dr. Antonio Loureiro Borges 5, Arquiparque - Miraflores, Apartado 300, 2795 LINDA-A-VELHA, Tel. (01)4163160/4163333, Fax. (01)4163174/4163366 Singapore: Lorong 1, Toa Payoh, SINGAPORE 1231, Tel. (65)350 2000, Fax. (65)251 6500 South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale, 2092 JOHANNESBURG, P.O. Box 7430, Johannesburg 2000, Tel. (011)470-5911, Fax. (011)470-5494 Spain: Balmes 22, 08007 BARCELONA, Tel. (03)301 6312, Fax. (03)301 42 43 Sweden: Kottbygatan 7, Akalla. S-164 85 STOCKHOLM, Tel. (0)8-632 2000, Fax. (0)8-632 2745 Switzerland: Allmendstrasse 140, CH-8027 ZURICH, Tel. (01)488 2211, Fax. (01)481 77 30 Taiwan: PHILIPS TAIWAN Ltd., 23-30F, 66, Chung Hsiao West Road, Sec. 1. Taipeh, Taiwan ROC, P.O. Box 22978, TAIPEI 100, Tel. (886) 2 382 4443, Fax. (886) 2 382 4444 Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd., 209/2 Sanpavuth-Bangna Road Prakanong, Bangkok 10260, THAILAND, Tel. (66) 2 745-4090, Fax. (66) 2 398-0793 Turkey: Talatpasa Cad. No. 5, 80640 GULTEPE/ISTANBUL, Tel. (0 212)279 27 70, Fax. (0212)282 67 07 Ukraine: Philips UKRAINE, 2A Akademika Koroleva str., Office 165, 252148 KIEV, Tel. 380-44-4760297, Fax. 380-44-4766991 United Kingdom: Philips Semiconductors LTD., 276 Bath Road, Hayes, MIDDLESEX UB3 5BX, Tel. (0181)730-5000, Fax. (0181)754-8421 United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409, Tel. (800)234-7381, Fax. (708)296-8556 Uruguay: Coronel Mora 433, MONTEVIDEO, Tel. (02)70-4044, Fax. (02)92 0601
Internet: http://www.semiconductors.philips.com/ps/ For all other countries apply to: Philips Semiconductors, International Marketing and Sales, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Telex 35000 phtcnl, Fax. +31-40-2724825 SCDS47 (c) Philips Electronics N.V. 1996
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
537021/1100/01/pp44 Document order number: Date of release: 1996 Jan 17 9397 750 00577

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